2010-2011 CSCE 681 AbstractsSpring 2011 AbstractsCSCE 681 Graduate Seminar:Overcoming Exascale Barriers
Dr. Bronis de Supinski
4:10 p.m., Wednesday January 19, 2011 AbstractExascale systems are currently projected to exist by 2018. The architectures of these systems, which will employ unprecedented levels of parallelism, will present numerous challenges. Many of these challenges are already becoming common in current systems but will become even more significant. For example, multicore chips not only imply increased parallelism but also bring reduced memory size per core and memory bandwidth per core due to cost considerations. Similarly, many exascale systems will feature accelerators, such as GPUs present in the Chinese Tianhe-1A system, the current number one on the Top500 list. Other challenges, such as debugging large-scale parallel jobs, have existed for several years but could become insurmountable due to the architectural changes of exascale systems. To overcome these challenges, programming models for large scale systems and the algorithms implemented in those models must change significantly. Further, we must adapt our system software and tools and their paradigms to the address the unprecedented concurrency and other architectural trends. In this talk, I will outline the overall strategy of Lawrence Livermore National Laboratory to address these challenges and detail some recent advances that contribute to that strategy. BiographyBronis R. de Supinski is the principal investigator and leader of the Exascale Computing Technlogies (ExaCT) project and the co-leader of the Advanced Simulation and Computing (ASC) program's Application Development Environment and Performance Team (ADEPT) at Lawrence Livermore National Laboratory (LLNL). He is also an Adjunct Associate Professor in the Department of Computer Science and Engineering at Texas A&M University. His research interests include high performance computer architectures, performance modeling and analysis, message passing implementations and tools, large-scale debugging, memory performance improvement, cache coherence and distributed shared memory, consistency semantics and programming models. Bronis earned his Ph.D. in Computer Science from the University of Virginia in 1998 and he joined LLNL's Center for Applied Scientific Compuiting (CASC) in July 1998. Currently, his projects include scalable debugging methods, investigations into mechanisms and tools to improve memory performance, applications of data mining techniques to tools for large-scale systems, resiliency techniques, a variety of optimization techniques and tools for MPI and several issues with OpenMP, including its memory model and tool support. He pursues the last set of topics as the Chair of the OpenMP Language Committee. Throughout his career, Bronis has won several awards, including the prestigious Gordon Bell Prize in 2005 and 2006. He is a member of the ACM and the IEEE Computer Society. Faculty Contact: Dr. Nancy Amato (amato [at] cse.tamu.edu) CSCE 681 Graduate Seminar:Electronic Voting Technology and Election Integrity: Landscape and ChallengesVideo of Dr. Shvartsman's presentation can be found here.
Dr. Alexander A. Shvartsman
4:10 p.m., Wednesday January 26, 2011 AbstractEntering the 21st century, our nation suddenly and belatedly came to the realization that the mechanisms and technologies supporting our elections were inadequate. The variety of paper-based, mechanical, and electronic voting processes and systems fell short of meeting sensible expectations for accurate and verifiable elections, and did not provide acceptable access for people with disabilities. Given the perceived inadequacies of the punch card and lever voting systems, many States adopted direct recording electronic (DRE) systems, with or without paper records, and chose optical scanning (OS) systems from a variety of vendors who ventured to satisfy the demand for new equipment. While the DRE systems provide potential advantages, such as user-friendly touch screens, assistance with vote validation, and elimination of preprinted ballots, these systems do not provide direct voter-verified paper trail (VVPT) and present voter authentication challenges. Moreover, elections conducted with paperless DRE systems are inherently not auditable. Several States that found themselves on the bleeding edge of this technology are now in the process of scrapping the recently procured DRE systems. It is estimated that over half a billion dollars worth of DRE machines were scrapped. The OS (optical scan) tabulation systems provide an auditable VVPT alternative, although they are not as user-friendly and they do not provide better access for people with disabilities. Another major area of concern is that broadly deployed DRE and OS systems were designed with insufficient regard for software quality, system security, and overall dependability. Essentially all systems in use today can be compromised by modestly-informed but determined attackers. In some cases a voting terminal can be compromised in a matter of minutes if it, or its removable storage device, is left unattended. Successful attacks can be undetectable, be time-sensitive, and can swap votes cast for candidates or subtly redistribute the votes. Systems that use central tabulation of results are left open to a variety of devastating attacks. In this talk we discuss these issues, make practical recommendations aimed at increasing the integrity of elections, including both technical and procedural aspects, such as chain of custody procedures, audits of technology, random hand-counted audits, and recounts. We present the results of evaluating several voting systems (including some used in Texas), and we discuss our approach to designing and conducting technological pre- and post-election audits now used in Connecticut. We conclude with directions for future work. BiographyAlexander Shvartsman is a Professor of Computer Science and Engineering at the University of Connecticut. He received his B.S. from Stevens Institute of Technology in 1979 and a M.S. from Cornell University in 1981, both in Computer Science. Deciding that an academic career was clearly not for him, he went to industry, working at Bell Labs and Digital Equipment Corp., first as an engineer, then as a manager. In 1988 he decided that an industrial career was clearly not for him and he entered the doctoral program at Brown University, earning his Ph.D. in 1992. Subsequently he did his post-doctoral study at MIT, then joined the Computer Science & Engineering faculty at the University Connecticut. His research in distributed and parallel computing, fault tolerance, formal methods, and electronic voting has been funded by numerous grants, including the NSF Career Award. Alex authored over 125 research papers and two books. He chaired and served on program committees of many conferences in distributed computing. He currently also directs the UConn Center for Voting Technology Research, nationally recognized for leadership work in integrity of electronic voting systems. Lastly, he is a Vigneron d'Honneur of Jurade de Saint-Emilion Faculty Contact: Dr. Jennifer Welch (welch@cse.tamu.edu) CSCE 681 Graduate Seminar:Building and Evaluating Creative Interaction
Dr. Celine Latulipe
4:10 p.m., Wednesday February 2, 2011 AbstractVisionaries in Computer Science have long seen the computer as a tool to augment our intellect. However, while it is relatively straightforward to measure the impact of a tool or technique on task efficiency for well-defined tasks, it is much more difficult to measure computers' impact on higher-level cognitive processes, such as creative processes. In my own research in Human-Computer Interaction, I create novel interaction techniques, but run up against the problem of trying to demonstrate how these tools positively impact higher-level processes such as creativity, expressiveness and exploration. In this talk, I first present a variety of interaction techniques that I have developed, and I then describe a new survey metric, the Creativity Support Index (CSI), that we have developed to help researchers and designers evaluate the level of creativity support provided by various systems, tools or interfaces. I will discuss what has been learned during the process of creating this survey and its usage in three different studies. The Creativity Support Index is one of the very first indices to support any evaluation of a computer system's impact on higher-level cognitive work. I will discuss the CSI within the context of my longer term goal to develop a suite of tools (including biometric tools) that provide both stronger analytical power, and a fundamental framework for evaluating computational support for creative activities, engagement and aesthetic experience. BiographyDr. Celine Latulipe has a PhD in Computer Science from the University of Waterloo in Canada. She is an Assistant Professor of Human-Computer Interaction in the Department of Software and Information Systems in the College of Computing and Informatics at UNC Charlotte. Dr. Latulipe has long been fascinated by two-handed interaction in the real world, and the absence of it in the human-computer interface. She has developed numerous individual and collaborative two-handed interaction techniques and these have blossomed into an exploration of creative expression. Dr. Latulipe works on projects with choreographers, dancers, artists and theatre producers to better understand creative work in practice and how technology may play a role in supporting and evaluating creative work practices. Currently, Dr. Latulipe is working on the Dance.Draw project, funded by an NSF CreativeIT grant. Faculty Contact: Dr. Tracy Hammond (hammond@cse.tamu.edu) CSCE 681 Graduate Seminar:A New Era for the Convergence of Network Centric and Data Centric ComputingVideo of Dr. Du's presentation can be found here.
Dr. David Du
4:10 p.m., Monday February 7, 2011 AbstractThe Internet today has grown to an enormously large scale. Devices large and small are connected globally from anywhere on the earth. Therefore, we can argue that we are in a network centric era. With the rapid advancement of technology, we now also have cheap and small devices with high computing power and large storage capacity. These devices are designed to improve our daily life by monitoring our environment, collecting critical data, and executing special instructions. These devices have gradually become a dominant part of our Internet. Many imaging, audio and video data are converted from analog to digital. As a result, unprecedented amount of data are collected by these devices and are available via Internet. How to manage and look for the desired information becomes a great challenge. Therefore, we can certainly also say that we are in a data centric era. In this talk, we will examine the challenges in the convergence of both network centric and data centric computing. At the same time, many emerging applications like service-oriented, security and real-time demand much better support than the current Internet can offer. To meet these challenges, National Science Foundation also has started a major effort, called GENI (Global Environment for Networking Innovations) to resign the Internet from scratch. However, how the future Internet should look like is still undetermined. In this talk, we will present a vision of content addressable future Internet. What are the essential changes in data representation, information retrieval, storage systems and networking design will be discussed. We believe an object-oriented intelligent storage is an essential part of the solution to this new computing and communication environment. We will also present a number of research projects that are currently under investigation in our NSF I/UCRC Center on Intelligent Storage. These projects include data deduplication, long-term data preservation, data center power management, and solid state drives. BiographyProfessor Du has authored or co-authored more than 160 technical papers, including 75 refereed journal publications, and in his research areas he has graduated 34 Ph.D. students in the last 19 years. He is a IEEE Fellow and a Fellow in the Minnesota Supercomputer Institute. He is the editor of Parallel and Distributed Practices and International Journal on Cluster Computing, and was also an editor of IEEE Transactions on Computers from 1992 to 1998. He has served as conference chair and program committee chair for several conferences in multimedia and database areas. Dr. Du received research grants from the National Science Foundation and companies such as 3M, Northern Telecom, Dell, IBM, Seagate, and Unisys. In 2004, the Digital Technology Center at the University of Minnesota awarded him the Outstanding Service Award. Dr. Du received his PhD from the University of Washington (Seattle) in 1981. Faculty Contact: Dr. Riccardo Bettati (bettati [at] cse.tamu.edu) CSCE 681 Graduate Seminar:Toward Memory-Efficient Matrix Algebra Algorithms and SoftwareVideo of Dr. Jessup's presentation can be found here.
Dr. Elizabeth R. Jessup
4:10 p.m., Wednesday February 9, 2011 AbstractWhile competing matrix algebra algorithms have traditionally been compared in terms of floating-point operation costs, it has long been known that the reduction of memory access costs is essential to attaining good performance. Achieving such improvements is, however, becoming increasingly difficult. Advancements in microprocessors and in numerical algorithms themselves mean that arithmetic costs are decreasing and that memory costs can predominate even in modestly sized computations. We will give an overview of our work on algorithm and tool development for reducing memory costs in matrix algebra software. We will begin with a review of an innovative block algorithm for solving linear systems that, together with special programming techniques, delivers significant speedups when compared to standard methods. We will proceed to a tool designed to evaluate memory traffic given MATLAB prototypes that we have used to improve the efficiency of an important climate modeling code. We will conclude with an introduction to the Build to Order compiler that automates the optimization of matrix algebra kernels, thus simplifying the production of high-performance implementations. BiographyLiz Jessup is Professor of Computer Science at the University of Colorado at Boulder. She earned her B.A. in mathematics at Williams College and her Ph.D. in computer science at Yale University. Her research concerns the development of efficient algorithms and software for matrix algebra problems. At UCB, Liz has been actively involved in undergraduate education, beginning with her role as co-creator of an award-winning, NSF-funded undergraduate curriculum in high-performance scientific computing. She has also worked to promote the participation of women in computing and has carried out research into factors influencing women's choices to study computing. She has held a variety of administrative positions at UCB including serving as department chair in 2006 and 2007. CSCE 681 Faculty Contact: Dr. Nancy Amato (amato [at] cse.tamu.edu) CSCE 681 Graduate Seminar:Testing High-Performance Integrated CircuitsVideo of Dr. Walker's presentation can be found here.
Dr. Hank Walker
4:10 p.m., Monday February 14, 2011 AbstractFollowing their manufacture, integrated circuits (ICs) are tested to verify that they meet their specifications, in terms of function, performance and reliability over the specified voltage and temperature range. Since the cost of manufacturing a transistor continues to fall exponentially, the cost of testing this transistor must also fall at the same rate, or Moore's Law will come to an end. ICs have a speed and power distribution. A key test challenge is dividing up this population into speed and power "bins," with low-power ICs targeted at mobile products, and high-performance ICs targeted at servers. Binning has traditionally been done using hand-written functional tests. The high cost of developing and applying such tests has limited their use to high-volume, high-end products, such as microprocessors. Our research focuses on automatically generating delay tests that have high correlation with functional test results, so that such tests can be applied to a wider class of products and at lower cost. We have developed an approach known as K Longest Paths Per Gate (KLPG) that tests the K longest sensitizable paths through every line in the circuit, while controlling power supply noise and signal crosstalk. We have developed a fast test pattern reordering approach that achieves near constant power dissipation during test, which simplifies temperature control. Our current research focuses on operating the chip in a pseudo-functional manner in order to produce power supply noise that is closer to that produced during functional test. Some experimental results on AMD microprocessors will be shown. BiographyDuncan M. (Hank) Walker is professor and graduate advisor in the Department of Computer Science and Engineering. He has been a member of the Texas A&M faculty since 1993, serving in the past as associate department head and in the Faculty Senate. He was previously a research faculty member in the Department of Electrical and Computer Engineering at Carnegie Mellon University, where he was assistant director of the SRC-CMU Research Center for Computer-Aided Design (now Center for Silicon Systems Integration). He has worked at Hughes Aircraft, Digital Equipment and IBM. His research interests include defect-based test, delay test, power supply noise, IDDQ test, and yield modeling. He holds a BS in engineering from Caltech, and MS and PhD in computer science from Carnegie Mellon. He has chaired a number of conferences, including the International Workshop on Defect and Data Driven Testing (D3T), and the International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), and is an associate editor of the IEEE Transactions on Computer-Aided Design of Circuits and Systems. His recent keynote addresses have been at the Southwest DFT Conference and the DFTS Symposium. He has graduated 18 doctoral and 33 masters students. CSCE 681 Faculty Contact: Dr. Nancy Amato (amato [at] cse.tamu.edu) CSCE 681 Graduate Seminar:Pregel: A Large-scale Distributed Graph-processing System
Dr. James C. Dehnert
4:10 p.m., Monday February 28, 2011 AbstractMany practical computing problems involve large graphs. Well-known examples include the Web graph and various social networks. The scale of these graphs — in some cases billions of vertices and trillions of edges — poses challenges for their efficient processing. Pregel provides a programming model and distributed infrastructure suitable for the processing of extremely large graphs. Programs are expressed as a sequence of iterations. In each iteration a vertex can receive messages sent in the previous iteration, send messages to other vertices, modify its own state and that of its outgoing edges, or mutate graph topology. This vertex-centric approach is flexible enough to express a broad range of algorithms. The model has been designed for efficient, scalable, and fault-tolerant implementation on clusters of thousands of commodity computers. Details related to distribution are hidden behind an abstract API, and the implied synchronicity of the model makes it easy to reason about Pregel programs. The result is a framework for processing large graphs that is expressive and easy to program. The talk will highlight the programming API, with experimental results from an implementation that illustrate the scalability of the model. BiographyDr. James C. Dehnert received his Ph.D. in applied mathematics from UC Berkeley. After extensive work on compilers at ROLM, Cydrome, SGI, and Transmeta, especially code generation for high performance computing, he is now working at Google on distributed infrastructure. CSCE 681 Faculty Contact: Dr. Lawrence Rauchwerger (rwerger [at] cse.tamu.edu) CSCE 681 Graduate Seminar:Simulating Multicores on Multicores — A Challenge to Build Fast Parallel SimulatorsVideo of Dr. Yew's presentation can be found here.
Dr. Pen-Chung Yew
4:10 p.m., Monday March 7, 2011 AbstractAs multicores become the de facto machine organization of almost all computer platforms today, computer architects are faced with an unprecedented challenge of designing future generations of multicores that will have twice as many cores in each new generation (due to Moore's Law) with ever stricter power budget (due to power wall), and with an increasing complexity of possible machine organizations, e.g. heterogeneous vs. homogeneous multicores, as well as a milieu of possible interconnect schemes. Traditionally, computer architects use cycle-accurate architectural simulators to study various detailed design tradeoffs at the architectural level, e.g. cache hierarchy and coherence schemes, instruction pipeline design, and power estimate, before logic and circuit designs are ensued. Such simulations typically have a slow down factor of more than 1000X (i.e. 1 minute of native execution time, will take one day in a cycle-accurate simulation). With the increasing number of cores to simulate, the slowdown factor has shown to be increased more than linearly because of the needed synchronization between simulated cores. Many attempts have been tried to run such simulations on parallel machines in the past with limited success due to the long communication delay between processors. However, with the availability of multicores, there is an opportunity for speeding up such simulations. On the other hand, system and application software developers need a platform to program, debug and test their software long before the new machine become available to get their software ready when hardware is done. A virtual platform that could emulate the new machine functionally for such purposes will be extremely useful. Such a functional emulator traditionally has a slow down factor of more than 10X. There are very few efficient parallel functional emulators for multicores right now. More recent system virtualization uses very similar techniques to allow guest application binary in one instruction set to be run on a host platform with a different instruction set. The core technology is dynamic binary translation. In this research, we are exploring new approaches using compiler techniques to speedup such simulation/emulation/virtualization tasks for multicores on multicores. The main idea is to explore phase behavior and dynamic binary translation and optimization techniques to allow these tasks to run more efficiently with a good speedup on multicore platforms. BiographyPen-Chung Yew has been the Director of the Institute of Information Science, Academia Sinica since 2008. He is currently on leave from the Department of Computer Science in the University of Minnesota at Twin Cities. He served as the Head of the Department of Computer Science and Engineering in the University of Minnesota and the holder of the William-Norris Land-Grant Chair Professor between 2000 and 2005. He was on the faculty of the Department of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign, and was an Associate Director of the Center for Supercomputing Research and Development (CSRD) before joining the University of Minnesota in 1994. From 1991 to 1992, he served as the Program Director of the Microelectronic Systems Architecture Program in the Division of Microelectronic Information Processing Systems at the National Science Foundation, Washington, D.C. Pen-Chung Yew is a distinguished research fellow in Academia Sinica and an IEEE Fellow. He served as the Editor-in-Chief of the IEEE Transactions on Parallel and Distributed Systems between 2000 and 2005. He has also served on the program committee of many major conferences. He was a co-chair of the 1990 International Conference on Parallel Processing (ICPP), a general co-chair of the 1994 International Symposium on Computer Architecture (ISCA), the program chair of the 1996 International Conference on Supercomputing (ICS), a program co-chair of the 2002 International Conference on High Performance Computer Architecture (HPCA), a program co-chair of 2004 Asian-Pacific Computer Systems Architecture Conference (ACSAC), the general chair of 2006 International Conference on Parallel and Distributed Systems (ICPADS), program chair of 2010 International Conference on Parallel Processing (ICPP), and the program chair of 2011 ACM SIGPLAN Annual Symposium on Principles and Practices of Parallel Programming (Ppopp). CSCE 681 Faculty Contact: Dr. Nancy Amato (amato [at] cse.tamu.edu) CSCE 681 Graduate Seminar:Integrated Circuits in 32 nm and Beyond: Fully-Depleted Silicon-on-Insulator (FDSOI) CMOS a Better Option than Bulk CMOS
Dr. Andrei Vladimirescu
4:10 p.m., Wednesday March 23, 2011 AbstractAs technologies scale down into the deca-nanometer range, the benefits of linear scaling in terms of speed and power consumption are jeopardized by fundamental limitations such as increased leakage and variability. As a result, the circuit operating power does not scale any more because of the quasi-fixed supply voltage VDD, which has become a limiting factor for battery life in mobile applications. To compensate the device limitations and continue increasing the speed of low-power applications in the current Bulk-CMOS technology, multi-VDD domains, multi-threshold (VT) processes and power management techniques are employed with growing challenges at every new technology node. For the 32nm node and below, several new MOS device structures such as double- or multi-gate with new gate and insulator materials are being investigated to overcome the above issues. The Ultra-Thin Body and Buried oxide (UT2B) Fully-Depleted (FD) Silicon-On-Insulator (SOI) MOS transistor with a high-κ metal gate stack and undoped channel, is a promising candidate for ultra-low voltage and ultra-low power applications. This presentation will address the advantages of multi-VT UT2B FDSOI CMOS compared to today's Bulk-CMOS for low-power applications. The design of SRAMs operating at a supply of VDD=0.5V and improved stability in UT2B FDSOI CMOS will be highlighted along with performance characteristics obtained on fabricated structures in 32 nm. BiographyAndrei Vladimirescu is Professor of Electrical Engineering and Computer Science at the Institut Superieur d'Electronique de Paris and Visiting Professor at the University of California at Berkeley, associated with the Berkeley Wireless Research Center. He was part of the SPICE development team at UC Berkeley and in 1981 wrote the first parallel version called CLASSIE. His research activities are in the areas of circuit simulation and modeling, low-power and ultra-low-voltage (ULV) design and modeling, analog and RF circuit design, new devices, modeling and optimization. Professor Vladimirescu is the author of "The SPICE Book" published by J. Wiley and Sons in 1994, and, author and co-author of over 50 journal and conference papers on circuits, device modeling and circuit simulation. He serves on the TPC of the European Solid-State Circuits Conference (ESSCIRC) and is a member of the editorial board of the BioNanoScience Magazine. CSCE 681 Faculty Contact: Dr. Lawrence Rauchwerger (rwerger [at] cse.tamu.edu) CSCE 681 Graduate Seminar:The End of Anonymity, The Beginning of Privacy
Vitaly Shmatikov
4:10 p.m., Monday March 28, 2011 AbstractThe Internet economy relies on the collection and aggregation of personal data on an ever-increasing scale. Information about our tastes, purchases, searches, browsing history, social relationships, health history, genetics, and so forth is shared with advertisers, marketers, and researchers, who use it to predict individual behavior and provide personalized product offerings, recommendations, and even clinical treatments. I will survey privacy issues caused by massive aggregation of personal information. After demonstrating that the existing methods for "anonymizing" the data fail to provide meaningful privacy protection, I will describe new approaches to privacy-preserving computation. This includes Airavat, a new system for large-scale data analysis which integrates mandatory access control and differential privacy. BiographyVitaly Shmatikov is an associate professor at the University of Texas at Austin. His research focuses on security, privacy, and formal verification methods for secure systems and protocols. Vitaly was the recipient of the 2008 PET Award for Outstanding Research in Privacy Enhancing Technologies. CSCE 681 Faculty Contact: Dr. Guofei Gu (guofei [at] cse.tamu.edu) CSCE 681 Graduate Seminar:Debugging Patterns
Robert Metzger
4:10 p.m., Wednesday April 6, 2011 AbstractThe patterns approach to software, derived from the work of architect Christopher Alexander, has been used since the mid-90's to systematize various aspects of software engineering. It has been applied to topics as varied as objected-oriented class design and user interface description. This talk presents a comprehensive pattern taxonomy of software debugging. The taxonomy of Debugging Patterns comprises three main categories. Analysis Patterns are used up to the point where the defective part of the system is identified. Explanation Patterns are used once the defective part of the system is identified, and enable the programmer to make a correction. Prevention Patterns are used both before a specific defect behavior is identified, and after the flawed part of the system pertaining to a specified defect behavior is identified and corrected. The taxonomy includes both patterns and anti-patterns pertaining to debugging. The talk will explain the pattern hierarchy, the pattern template used to describe debugging patterns, and provide examples of common members of each genus of the taxonomy. BiographyRobert Charles Metzger is a senior engineer who designs optimizing compilers at Convey Computer Corp. Convey is a venture-capital funded company in Richardson, TX, which sells adaptive, energy-efficient hybrid-core computers for the high performance computing marketplace. For the past 25 years, Metzger has developed and managed the development of compilers, programming tools, and system administration software for high performance computers at Convex Computer Corp., the Hewlett-Packard Company, and now at Convey. He is the author of Debugging by Thinking: A Multidisciplinary Approach (Elsevier Digital Press, 2004) and co-author of Automatic Algorithm Recognition and Replacement: A New Approach to Program Optimization, (MIT Press, 2000). CSCE 681 Faculty Contact: Dr. Lawrence Rauchwerger (rwerger [at] cse.tamu.edu) CSCE 681 Graduate Seminar:Non-Facial and Non-Verbal Affective Expression for Appearance-Constrained Robots
Dr. Cindy L. Bethel
4:10 p.m., Monday April 11, 2011 AbstractNon-facial and non-verbal methods of affective expression are essential for naturalistic social interaction in robots that are designed to be functional and lack expressive faces (appearance-constrained) such as those used in search and rescue, military, industry, and law enforcement applications. This research identifies five main methods of non-facial and non-verbal affective expression (body movements, postures, orientation, color, and sound) and ranks their effectiveness for appearance-constrained robots operating within the intimate (contact - 0.46 m), personal (0.46 - 1.22 m), and social (1.22 - 3.66 m) proximity zones of a human corresponding to inter-agent distances of approximately three meters or less. This leads to design guidelines for retroactively adding affective expression through software to a robot with little or no physical modifications. To confirm that humans respond more favorably to an affective appearance-constrained robot, a study was conducted with 128 participants and two robots (iRobot Packbot Scout and an Inuktun Extreme-VGTV) in a high fidelity simulated disaster site. Four methods of evaluation were utilized: (1) self-assessments, (2) psychophysiological measures (EKG, abdominal respiration, thoracic respiration, blood volume pulse, skin conductance response), (3) video recording from four different camera perspectives that are currently being coded for behavioral responses, and (4) an audio recorded follow-up interview. This is the largest and most comprehensive controlled study performed in HRI to date. Details of the study design, implications for HRI and robot design, results, and video will be presented. BiographyCindy is a NSF/CRA/CCC Computing Innovation Postdoctoral Fellow and Postdoctoral Associate in the Social Robotics Laboratory at Yale University. She is currently working with Brian Scassellati as her fellowship mentor. She was a National Science Foundation Graduate Research Fellow and the recipient of the 2008 IEEE Robotics and Automation Society Graduate Fellowship. She graduated in August 2009 with her Ph.D. in Computer Science and Engineering from the University of South Florida. Her research interests are in Human-Robot Interaction (HRI), affective computing, robotics, Human-Computer Interaction (HCI), artificial intelligence, psychology, experimental design, and statistical analysis. She graduated with a B.S. in Computer Science Summa Cum Laude from the University of South Florida. She was awarded the King O'Neal Scholar award, the Computer Science and Engineering Outstanding Graduate Award, and the Engineering Alumni Society Outstanding Senior of the Year Award. CSCE 681 Faculty Contact: Dr. Robin Murphy (murphy [at] cse.tamu.edu) CSCE 681 Graduate Seminar:Why Make Robots Humanlike?
David Hanson, Ph.D.
4:10 p.m., Wednesday April 13, 2011 AbstractPeople are drawn to humanlike robots, and it is a common, apparently natural, tendency to make robots in our image. On the other hand, humanlike identity in robots may seem threatening or unsettling to some people, and they may raise user expectations higher, to levels that are difficult to address given the limitations of today's intelligent software.Since non-humanoid robots can be extremely useful, and humanlike robots are so challenging, is the quest for humanlike intelligence in machines worth the trouble? They certainly are. Robotics researchers should aspire as grandly and broadly as possible. Human beings represent our best standard for intelligence, creativity, understanding, and compassion. While these may be daunting targets for robot researchers, they stand as noble and worthy aspirations for our robots. Even as we struggle to unlock humanlike capacities for our robots, the incremental progress towards such goals can still result in captivating art, useful treatments such as for autism spectrum disorders, and powerful scientific research into mysteries of human nature. BiographyDr. David Hanson develops extremely lifelike robots. With expressive robotic faces on walking robot bodies, cognitive A.I., human-robot interaction, aesthetics and perception, sculpture, advanced actuators, and material science, Hanson strives to bring robots to life, in ways both helpful and loveable. A former Walt Disney Imagineer, Hanson received awards from NASA, NSF, Innovator of the Year, and Cooper Hewitt Design Triennial, and appears in press attention from WIRED, the New York Times, BBC and others. Hanson invented or co-invented numerous bio-inspired technologies, including patented lipid-bilayernanotech for naturalistic skin, expressive face mechanisms, and neurocognitive-inspired algorithms for machine cognition, publishing over 20 peer-reviewed papers with IEEE, Science, Springer, Cog Sci, and SPIE, chapters in 4 books, and coauthoring a book with JPL senior scientist YosephBar-Cohen. Hanson received his Ph.D. from the University of Texas at Dallas in Aesthetic Studies/ Interactive Arts and Engineering, and holds a BFA in film/video/animation from Rhode Island School of Design. In 2003, David Hanson founded Hanson Robotics, aiming to realize robots as friends. Since then, Hanson and team introduced a series of lifelike robots, including Albert-Hubo(in collaboration with KAIST), and the small Zeno RoboKind, a walking expressive platform for research and consumers. Hanson's robots serve research in cognitive science, autism treatment, and robotics research at institutions including JPL, Cambridge University, KAIST, UCSD, and the University of Geneva, U. Pisa, and the Autism Treatment Center in Dallas.In 2009, Hanson founded the nonprofit Apollo Mind Initiative to accelerate worldwide, open collaboration on realizing friendly A.I. CSCE 681 Faculty Contact: Dr. Robin Murphy (murphy [at] cse.tamu.edu) CSCE 681 Graduate Seminar:Robot Enabled Cloud: Robots as Just Another Web Service
Dr. Chad Jenkins
4:10 p.m., Wednesday April 20, 2011 AbstractReproducibility and interoperability are critical needs for a thriving ecosystem of robotics research and development. The combination of off-the-shelf robotics platforms, cloud computing, and standardized interfaces and protocols has the power to enable vast new applications for robotics that can be accessed as web services. In this talk, I cover our recent work, building on the Robot Operating System (ROS), for developing robot web applications purely through JavaScript/HTML, web-scale robot learning, and a PR2 Remote Lab for common decentralized experimentation. This work serve as a step towards web services as a common user interface for complete integrated robotic systems. BiographyOdest Chadwicke Jenkins, Ph.D., is an Associate Professor of Computer Science at Brown University. Prof. Jenkins earned his B.S. in Computer Science and Mathematics at Alma College (1996), M.S. in Computer Science at Georgia Tech (1998), and Ph.D. in Computer Science at the University of Southern California (2003). Prof. Jenkins was selected as a Sloan Research Fellow in 2009. He is a recipient of the Presidential Early Career Award for Scientists and Engineers (PECASE) for his work in physics-based human tracking. He has also received Young Investigator awards from the Office of Naval Research (ONR) for his research in learning dynamical primitives from human motion, the Air Force Office of Scientific Research (AFOSR) for his work in manifold learning and multi-robot coordination and the National Science Foundation (NSF) for robot learning from multivalued human demonstrations. His research addresses problems in robot learning and human-robot interaction, primarily focused on robot learning from demonstration, as well as topics in computer vision, machine learning, and computer animation. CSCE 681 Faculty Contact: Dr. Nancy Amato (amato [at] cse.tamu.edu) CSCE 681 Graduate Seminar:Deficiencies & Vulnerabilities in Commercial Anti-Malware Programs
Dr. Jose Morales
4:10 p.m., Monday April 25, 2011 AbstractCurrent commercial anti-malware programs (CAmps) are marketed as effective and reliable security solutions for desktops, laptops and and mobile devices. The user trusts the CAmp to protect their system from malware infection and expects the system to run in a clean state. But what if the CAmp possesses deficiencies and vulnerabilities resulting in below average detection and treatmeant, and facilitated functionality compromises? In this talk I divide a CAmp into three main sections: detection, treatment, and self defense. For each section I will present deficiencies and exploitable vulnerabilities allowing CAmp compromise. These compromises result in misleading both the CAmp and user about the actual protection status of their system and allows malware to freely execute without being erradicated or isolated. Countermeasures are suggested but in some cases are too difficult to implement leaving open several future research questions. BiographyJose Andre Morales is a Research Assistant Professor for the Institute of Cyber Security in the University of Texas at San Antonio. His research area is computer virology with a current focus on the analysis and behavior-based detection of malware, anti-malware program evaluation, assessing malicious intent, and implementing biological defense mechanisms into computer systems. He is a member of Sigma Xi, ACM and IEEE. He is also Co-founder and administrator of Hispanics in Computing, formerly called HispanicPhD. CSCE 681 Faculty Contact: Dr. Valerie Taylor (taylor [at] cse.tamu.edu) Fall 2010 AbstractsCSCE 681 Graduate Seminar (only required for new graduate students):
Graduate Orientation I: Overview of Department Resources & Contacts, Honor Code, and Student Organizations
|
| ||||
| ||||